CENTRALE LYON - Post-Doctoral Position Ferroelectric-Based Ternary Computing: From Circuit Design to System-Level Integration Scientific Context

<p class="MsoNormal" style="text-align:justify;">Energy efficiency remains one of the foremost challenges in modern computing, spanning from edge IoT devices to high-performance data centers. Conventional CMOS-based architectures are approaching fundamental physical limits, while the "memory wall" — data transfers between processor and memory accounting for 70 to 90% of total system energy — continues to worsen with the ever-growing demands of data-intensive workloads such as deep neural networks and signal processing pipelines.</p><p class="MsoNormal" style="text-align:justify;min-height: 1.7em;"></p><p class="MsoNormal" style="text-align:justify;">In-Memory Computing (IMC) has emerged as a disruptive paradigm to overcome these bottlenecks by embedding arithmetic operations directly within memory arrays, drastically reducing data movement. In this landscape, ferroelectric field-effect transistors (FeFETs) stand out as particularly compelling devices: fully compatible with standard CMOS fabrication processes, non-volatile, reconfigurable, and capable of storing intermediate polarization states — a property that naturally enables ternary logic within a single device.</p><p class="MsoNormal" style="min-height: 1.7em;"></p><p class="MsoNormal">The Post-Doctoral position will cover at least one of the following tasks:</p><p class="MsoNormal" style="text-align:justify;min-height: 1.7em;"></p><ul><li><p><strong>Design Standard Cell Technology Library</strong> based on FeFET devices developed at INL in order to be used with synthesis flow.</p></li><li><p><strong>Design and optimize ternary arithmetic units</strong> (multiply-accumulate units, adders, comparators) based on the FeFET ternary gate library developed within the project, targeting area, power, and timing closure under realistic process constraints.</p></li><li><p><strong>Develop and refine system-level models</strong> of FeFET-based ternary IMC units, abstracting circuit-level characterization results into architecture simulators, enabling design space exploration across the full heterogeneous system.</p></li><li><p><strong>Investigate hardware/software co-design strategies</strong> for mapping real-world applications — particularly convolutional neural networks (CNNs) and signal processing kernels — onto the ternary IMC fabric, exploiting approximate computing techniques to trade precision for energy efficiency.</p></li><li><p><strong>Assess and benchmark the energy, performance, and accuracy trade-offs</strong> of ternary IMC against binary CMOS and binary NVM-based IMC reference implementations, using both synthetic benchmarks and real application workloads.</p></li><li><p><strong>Contribute to the definition of a design methodology</strong> for ternary ferroelectric circuits, including EDA tool flows, cell library characterization guidelines, and design rules, with the aim of enabling broader community adoption.</p></li></ul><p style="min-height: 1.7em;"></p> <br> <p class="MsoNormal"><strong>Required Candidate Profile</strong></p><p class="MsoNormal" style="min-height: 1.7em;"></p><p class="MsoNormal">The ideal candidate holds a <strong>PhD in microelectronics, computer architecture, or a closely related field</strong>, and demonstrates at least one of the following hard skills:</p><p class="MsoNormal" style="min-height: 1.7em;"></p><ul><li><p><em>Circuit and architecture des