FPGA Engineer - Electronic Warfare

<h3><strong>About Us</strong></h3><p style="min-height:1.5em">Harmattan AI is a next-generation defense prime building autonomous and scalable defense systems. Following the close of a $200M Series B, valuing the company at $1.4 billion, we are expanding our teams and capabilities to deliver mission-critical systems to allied forces.</p><p style="min-height:1.5em">Our work is guided by clear values: building technologies with real-world impact, pursuing excellence in everything we do, setting ambitious goals, and taking on the hardest technical challenges. We operate in a demanding environment where rigor, ownership, and execution are expected.</p><p style="min-height:1.5em"></p><h2><strong>About the Role</strong></h2><p style="min-height:1.5em">As an FPGA Engineer within our Electronic Warfare team, you will design and implement the real-time digital signal processing that turns raw RF into actionable effect — from receiver channelization and threat detection through to jamming waveform generation. You will own the RTL at the heart of our EW and SIGINT systems, working hand-in-hand with the RF hardware, embedded software and algorithm teams to take a signal chain from concept and simulation to silicon, to the lab, and into the field.</p><p style="min-height:1.5em"></p><h2><strong>Responsibilities</strong></h2><ul style="min-height:1.5em"><li><p style="min-height:1.5em"><strong>RTL Design &amp; Implementation:</strong> Design and implement signal-processing datapaths in VHDL or SystemVerilog — digital down-conversion, channelizers, filtering, FFT and detection chains — from specification through to validation.</p></li><li><p style="min-height:1.5em"><strong>Real-Time DSP in Fabric:</strong> Implement detection, direction-finding, classification and waveform generation under hard latency and throughput budgets, translating algorithm intent into fixed-point hardware.</p></li><li><p style="min-height:1.5em"><strong>RF &amp; Data Converter Interfacing:</strong> Own the digital interface to the RF front-end — high-speed converters (JESD204B/C), multi-channel clocking, synchronization and calibration paths.</p></li><li><p style="min-height:1.5em"><strong>Hardware/Software Partitioning:</strong> Define the split between programmable logic and on-chip processors, and the register and streaming interfaces the embedded software team builds against.</p></li><li><p style="min-height:1.5em"><strong>Timing Closure &amp; Resource Budgets:</strong> Drive constraints, timing closure, and resource, power and thermal budgets on production hardware.</p></li><li><p style="min-height:1.5em"><strong>Bring-up, Integration &amp; Validation:</strong> Lead FPGA bring-up on new boards, bench validation against performance targets with RF instrumentation, and over-the-air testing alongside the systems team.</p></li><li><p style="min-height:1.5em"><strong>Technical Coordination:</strong> Collaborate across RF hardware, embedded, GNC and ML teams on system integration and technical interfaces.</p></li><li><p style="min-height:1.5em"><strong>System Reviews &amp; Documentation:</strong> Contribute to design and architecture reviews, maintaining consistency between requirements, design and testing.</p><p style="min-height:1.5em"></p></li></ul><h2><strong>Candidate Requirements</strong></h2><ul style="min-height:1.5em">