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System modelling Engineer
<p style="min-height: 1.7em;"></p><p><strong><span style="color:#222222">About Us</span></strong><span style="color:#222222"> : </span><span style="color:#000000">AI compute is hitting a hard physical wall, and memory bottlenecks are throttling the entire industry. Founded in October 2024 and backed by €57M in funding, Vertical Compute is solving this with proprietary Vertical Integrated Memory (VIM™) chiplets, making AI hardware faster, greener, and vastly more scalable. We are an interdisciplinary team transforming breakthrough semiconductor physics into commercial reality.</span></p><p><strong><span style="color:#222222">Why Now</span></strong><span style="color:#222222"> : </span><span style="color:#000000">After 18 months of intensive R&D, Vertical Compute has reached a critical inflection point. Our underlying technology is validated, and we have successfully met our core technical milestones. Armed with a proven technical data package and ongoing system studies, we are now shifting from pure R&D to active engagement with global enterprise customers. As we prepare for our next phase of scale and growth starting in 2027, joining us today means taking direct ownership of the hardware foundation that will power the next era of AI compute.</span></p><p style="min-height: 1.7em;"></p><p style="min-height: 1.7em;"></p><p style="text-align:justify;"><strong><span style="color:#222222">About the role: </span></strong></p><p style="text-align:justify;"><span style="color:#000000">We are looking for an expert System Modelling Engineer to drive the modelling, integration, and performance analysis of our advanced Vertical Compute / VIMx system memory architectures.</span></p><p style="text-align:justify;"><span style="color:#000000">In this role, you will be responsible for building robust SystemC models, integrating them onto the Palladium emulation platform, and benchmarking performance against an ideal SRAM baseline for cutting-edge AI applications.</span></p><p style="text-align:justify;min-height: 1.7em;"></p><p style="text-align:justify;"><strong><span style="color:#222222">Key Responsibilities:</span></strong></p><ul><li><p style="text-align:justify;"><strong><span style="color:#222222">System-Level Modeling</span></strong><span style="color:#222222">: Design, validate, and deliver robust SystemC software models for individual VIMx components and the broader memory hierarchy.</span></p></li><li><p style="text-align:justify;"><strong><span style="color:#222222">Multi-Bank Configurations</span></strong><span style="color:#222222">: Model and simulate complex multi-bank system memory configurations to evaluate latency, throughput, and system behavior.</span></p></li><li><p style="text-align:justify;"><strong><span style="color:#222222">Emulation Platform Integration</span></strong><span style="color:#222222">: Deploy and configure completed SystemC memory models onto the Cadence Palladium emulation platform.</span></p></li><li><p style="text-align:justify;"><strong><span style="color:#222222">Co-Simulation & Validation</span></strong><span style="color:#222222">: Ensure seamless interface and ope